The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a final metal contact of a dynamic random access memory (DRAM) device having a cylinder type capacitor.
Since dynamic random access memory (DRAM) devices have a high capacitance and can freely input and output data, the DRAM devices have been widely used. Each of the DRAM devices includes an access transistor and a cumulative capacitor. The data signal is received from the top electrode and bit line of the capacitor from an external circuit through a final metal contact.
FIG. 1 is a scanning electron microscope (SEM) micrograph illustrating a cross-sectional view of a typical DRAM device including a final metal contact.
A first inter-layer insulation layer ILD1 covering a bit line BL is formed over a substrate completed with a bit line formation process. Afterwards, a nitride-based etch stop layer SN STOP NITRIDE and a second inter-layer insulation layer ILD2 for forming a capacitor are formed over the first inter-layer insulation layer ILD1. Then, predetermined portions of the second inter-layer insulation layer ILD2 and the nitride-based etch stop layer SN STOP NITRIDE are selectively etched to form a plurality of contact holes (not shown). Thereafter, a plurality of bottom electrodes (i.e., storage nodes SN) of the capacitor are formed only inside the contact holes (not shown) The second inter-layer insulation layer ILD2 and the nitride-based etch stop layer SN STOP NITRIDE between the bottom electrodes are selectively removed. Accordingly, a plurality of cylinder type storage nodes SN, which are electrically isolated from each other, are formed in a region where the capacitors are to be formed.
A dielectric layer (not shown) is formed over the height difference of the second inter-layer insulation layers ILD2 and the storage nodes SN. A plate electrode PLATE, which is the top electrode of the capacitor, is formed over the dielectric layer to fill a plurality of empty spaces between the storage nodes SN. Accordingly, a DRAM cell capacitor is completed. Afterwards, an amorphous silicon (a-Si) layer (or a polysilicon layer) having different etch selectivity from the plate electrode PLATE is formed over the plate electrode PLATE as a passivation layer to protect the plate electrode PLATE.
Predetermined portions of the amorphous silicon (a-Si) layer, the plate electrode PLATE, and the dielectric layer are selectively etched; then a third inter-layer insulation layer ILD3 is formed over the resulting structure.
An etching process using a mask is performed to form a plurality of metal contacts M1C exposing predetermined upper portions of the plate electrode PLATE and the bit line BL.
However, while the etching process exposing the upper portion of the bit line BL is performed by using the identical etch gas (e.g., a mixture gas of C4F6, Ar and O2) used through the mask, a punch-through phenomenon ‘P’ in which a cavity is formed in the plate electrode PLATE may be produced. Since the depth from the third inter-layer insulation layer ILD3 to the upper portion of the bit line BL is greater than the depth from the third inter-layer insulation layer ILD3 to the upper portion of the plate electrode PLATE, the etching process to form the metal contacts M1C exposing the upper portion of the bit line BL continues even after the metal contacts M1C exposing the upper portion of the plate electrode PLATE is formed. Herein, reference denotation M1 denotes a final metal interconnection line.
FIGS. 2A and 2B are SEM micrographs illustrating a punch-through phenomenon typically produced within a titanium nitride (TiN) layer forming a top electrode (i.e., a plate electrode) of a capacitor. FIG. 2A illustrates a portion where the top electrode of the capacitor is exposed, and FIG. 2B illustrates a portion where a bit line is exposed.
As described above, if the punch-through phenomenon ‘P’ is produced in the plate electrode, the contact area between the final metal interconnection line (to be subsequently formed) and the plate electrode is reduced. Thus, the contact resistance between the metal interconnection line and the plate electrode may be increased.